This invention relates to a waveform encoder/decoder, or codec.
One general form of waveform encoder/decoder system is shown in FIG. 1 of the accompanying drawings. The system comprises a local encoder 1 having an input terminal 2 to which is applied a waveform, for example an audio waveform, to be encoded and an output terminal 3 which connects to a transmission path 4 which may be a radio or infra red link or a wire or optic link or similar. The output data at terminal 3 is in the form of a digital data stream. At the remote end, a decoder 5 decodes the digital data stream to reproduce at its output terminal 6 an estimate of the input signal at terminal 2 of the encoder.
The encoder 1 comprises a local decoder 7 which is identical to the remote decoder 5 and acts to reconstruct, from the output digital data stream, an estimate of the input signal at terminal 2. Assuming no transmission errors, the output of the local decoder 7 will be identical to that of the remote decoder 5 since they are both acting on the same data. The estimated input signal reconstructed by local decoder 7 is combined with the real input signal in a subtraction circuit 8 whose output error signal is passed to a quantiser 9. The subtraction circuit and quantiser compares the real input signal and the estimated input signal and outputs a digital word which, when acted upon by the local decoder 7, is such as to reduce the error between the estimated signal and the real signal. As already mentioned, the remote decoder 5, being identical to local decoder 7, and acting on the same digital signal, outputs at terminal 6 an estimated representation of the input signal at terminal 2.
In complex systems of the type illustrated in FIG. 1, both the quantiser and the decoder may be adaptive (variable feedback loop gain), and the data output may take the form of multi-bit words.
FIG. 2 of the accompanying drawings illustrates the so-called delta modulation system, which is probably the simplest implementation of the generalised system shown in FIG. 1. In the FIG. 2 arrangement, the subtraction circuit 8 takes the form of a comparator 10 which outputs a single data bit corresponding to the sign of the error. This is sampled by the quantiser 9 which takes the form of a D-type flip-flop 11. The sampling rate is determined by a system clock signal applied to the flip-flop 11 on line 12. The local decoder 7 takes the form of an integrator 13 which is driven by the digital data stream at output terminal 3. The loop is arranged in such a way that if the real input signal at terminal 2 is greater than the estimate, giving rise to a negative error signal, then a logic 1 bit is output, which latter will cause the integrator 13 to slew in a positive direction, thus reducing the error. In the event that the real input signal is less than the estimate, then the opposite occurs. Thus the estimated signal on line 14 is made to track the input signal at terminal 2. This tracking effect is illustrated in FIG. 3A, where the dotted line represents the input signal--for example a speech waveform--and the solid line shows the estimated signal outputted from the integrator 13. FIG. 3B shows the clock signal on line 12; FIG. 3c shows the digital data stream outputted from flip-flop 11 to the terminal 3.
The remote decoder 5 is realised as an integrator 15 identical to the integrator 13 so that, once again, (and assuming no transmission errors) the output signal at terminal 6 will be identical to that on line 14--i.e. the solid line in FIG. 3A.
There are a number of problems with this simple type of encoder, and two of these will now be described with reference to FIGS. 4 and 5 of the accompanying drawings. The problem illustrated in FIG. 4A is known as delta slope overload and arises when a section of the signal being encoded (shown by the dotted line) changes at too high a rate for the integrator 13 (whose output is shown by the solid line) this leading to an accumulative error illustrated by arrow A in FIG. 4A. The corresponding data stream signal is shown in FIG. 4B. The problem illustrated in FIG. 5A is known as delta idle pattern and arises when the input signal (dotted line) has such a small amplitude--for example a quiescent signal--that it falls below the integrator output steps. In these circumstances, the integrator output changes direction at each clock pulse as it attempts to follow the input signal, giving a triangular wave output signal (solid line) on line 14. The 101010 . . . pattern of the output data stream (FIG. 4B) is known as the idle pattern. It will be seen from FIG. 5A that the output signal is grossly in error when compared with the input signal.
It is clear that, with the simple system shown in FIG. 2, there is only a relatively small limited range of input signal amplitudes--above idle pattern and below slope overload--for which good encoding is achieved. FIG. 6 of the accompanying drawings is a plot of signal to noise ratio against input signal amplitude. The left hand slope represents degradation due to idle pattern noise; the right hand slope represents degration due to slope overload. The resultant acceptable dynamic range is too small for effective speech encoding.
FIG. 7 shows a known system designed to improve the dynamic range of the basic delta modulation encoder illustrated in FIG. 2. Note that only the encoder 1 is shown in FIG. 7, it being assumed, as explained above, that a further decoder identical to the local decoder 7 will be provided at the remote end of the transmission path 4.
In the FIG. 7 arrangement, the input to integrator 13 is multiplied by a variable factor so that the integrator exhibits a variable slew rate, and the feedback loop a variable gain. The factor is adjusted in accordance with the amplitude of the input signal: for a large input signal the factor is large and a high slew rate results. This enables the integrator output to be adapted to more closely follow signals which would otherwise have caused slope overload. For small input signals the factor is small and the slew rate reduces which acts to reduce the amplitude of the signal from the integrator in the presence of the idle pattern. Both these effects improve dynamic range.
In order to enable the remote decoder (not shown) to accurately reproduce the input signal, the information for these slew rate changes must come from the output bit stream at terminal 3. To achieve this a shift register 16 is used to count the data bits output from flip-flop 11. The clock system signal on line 12 is applied to the clock input of the register. Three gates 17, 18, 19 are connected at the output of the shift register and are arranged in such a way as to recognise when 4 successive identical bits (all 0's or all 1's) are output from flip-flop 11, this being reckoned to be representative of a slope overload condition--see FIG. 4B. The output from the gates is passed to a CR network comprising capacitor C1 and resistor R1 which produces a voltage which is used to control the slew rate. This is achieved in an analogue multiplier 20 which multiplies the voltage on capacitor C1 with that on the output line from flip-flop 11 to produce an output voltage which sets the slew rate of integrator 13.
In the absence of slope overload, the capacitor C1 discharges to some minimum voltage which thus sets the minimum slew rate of integrator 13. The circuitry is often modified by means, not shown, to give a fast increase and a slow decrease in gain, in order to match the characteristics of speech.
The main problem with the circuitry shown in FIG. 7 is that the analogue multiplier is difficult to implement and is subject to such variables as component tolerances as it is an analogue circuit. As a result, it is very difficult to implement an identical decoder at the remote end, and the system is thus subject to errors.